1. Field of the Invention
The invention is directed to a circuit arrangement for discharging at least one circuit node, to an integrated circuit, and to a method for discharging at least one circuit node.
In integrated circuits, many circuit nodes have a comparatively great capacitance on which charges are stored during the operation of the circuit. A typical example of such a circuit node is the gate of an MOS (metal oxide semiconductor) transistor, whose capacitance is dependent on the channel length L and channel width W of the transistor.
After a supply voltage of an integrated circuit has been switched off, the charges stored on the circuit nodesxe2x80x94on their capacitances to be more precisexe2x80x94usually flow off. Dependent on the size of the capacitance of a circuit node and the size of the resistance of a path for the charge amounts to flow off, it can last a number of seconds until charges are no longer stored on the circuit node, i.e. until the capacitance of the circuit node has completely discharged.
Without additional circuit-oriented techniques, capacitances of circuit nodes frequently discharge via parasitic paths of the circuit that usually exhibit a very high resistance. As a result thereof, the discharge lasts very long; and it can lie in the range of minutes or even hours. In some integrated circuits, particularly from security-sensitive areas of employment such as, for example, automotive technology, however, it is usually undesired that the circuit nodes discharge slowly (for example, in the millisecond range).
A number of circuitxe2x80x94oriented methods are known from the Prior Art that enable a more or less fast discharge of circuit nodes after the supply voltage of an integrated circuit has been switched off.
What is probably the simplest circuit for discharging a circuit node is shown in FIG. 1. The discharge of a charge stored on a capacitance Cnode of the circuit node that corresponds to a voltage Vnode thereby occurs via a passive resistor Rpd as a discharge current Idischarge. Given a disconnect or an outage of the supply voltage, the charges stored on the capacitance Cnode can flow off over the passive resistor Rpd because of its self-conducting property.
Particularly given an integration, however, the resistor is subject to two contradictory demands. First, it should be high-impedance enough so that the integrated circuit is not additionally loaded and the power consumption remains in limits. During operation of the circuit, a current always fundamentally flows across the resistor. On the other hand, it must be low-impedance enough for an integration and, moreover, must be dimensioned such that the voltage Vnode stored on the capacitance Cnode can be discharged as quickly as possible. The integration of such resistors, however, is very surface-intensive and is therefore cost-unbeneficial and is also not possible at all in some semiconductor technologies.
The circuit for discharging a circuit node that is shown in FIG. 2 was therefore developed. In this circuit, the passive resistor has been replaced by an enhancement PMOS transistor. The gate terminal and the drain terminal of this transistor are connected to ground. The transistor can be integrated far more easily than the passive resistor. Above all, it requires far, far less surface. The voltage Vnode to be discharged is present at the source terminal of the transistor, this voltage essentially corresponding to the charges stored on the capacitance Cnode. The discharge current discharge flows off to ground via the channel.
What is disadvantageous about this circuit, however, is that the discharge event only lasts until the voltage at the source terminal has reached the threshold voltage of the MOS transistor and the transistor consequently becomes high-impedance. In other words, the transistor becomes extremely high-impedance and inhibits when the gate-source voltage falls below the threshold voltage. A residual charge thus remains stored on the capacitance Cnode and this can only flow off on the basis of leakage currents, but not across the inhibited transistor. The discharge by means of leakage currents, however, lasts a number of minutes.
Another circuit for discharging voltage nodes is shown in FIG. 3. Here, the capacitance of the circuit node is discharged via a depletion MOS transistor. The depletion MOS transistor can also be a JFET (unction field effect transistor). What is thereby essential is that such transistors are conductive in a non-supplied condition and inhibit in a supplied condition. What is understood by unsupplied condition is a voltage-free condition and what is understood by a supplied condition is a normal operating condition in which a supply voltage is present at the circuit.
The transistor is thus of the self-conducting type. This is achieved by an implanted channel. However, the transistor becomes more expensive as a result thereof since an additional process step is required in the manufacture. Moreover, the voltage at the gate terminal or back gate terminal of the transistor must exceed the voltage at the source terminal and drain terminal by what is referred to as the pinch-off voltage so that the transistor can inhibit. When, however, the circuit node to be discharged already lies at a voltage that roughly corresponds to the supply voltage, it can be necessary to boost the voltage at the gate terminal of the transistor to a voltage that is higher than the supply voltage. This is achieved by a charge pump 24. However, the complexity of the circuit is again increased as a result thereof.
FIG. 4 shows the typical discharge curves of a circuit node having a capacitance of 100 pF. The circuit nodexe2x80x94the capacitance thereof to be more precisexe2x80x94is charged to 15 V.
The lower discharge curve shows the discharge of the circuit node via a passive resistor, for example with the circuit shown in FIG. 1. The capacitance of the circuit node has been nearly completely discharged here after about 10 ms.
The upper curve represents the discharge with a circuit as shown in FIG. 2. The discharge occurs via an active PMOS resistor or transistor. The inhibiting effect of the resistance already shows up here when the charge stored on the capacitance or the corresponding voltage drops below the threshold voltage of the transistor. The circuit node cannot discharge completely with this circuit. A residual voltage remains.
In summary, the following can be said about the circuits known from the Prior Art.
Although a discharge via a passive resistor enables a nearly complete discharge of the capacitance of the circuit node, such a resistorxe2x80x94because of its large areaxe2x80x94cannot be integrated or can only be integrated with difficulty. Further, the resistor represents an additional load for the circuit in the normal operating condition since a current always flows across it. Finally, the discharge time is proportional to the value of resistance, as a result whereof long discharge times of the circuit node result. Moreover, each critical circuit node, i.e. each circuit node that has a great capacitance and/or that must be discharged quickly after a shut-off of the supply voltages, needs such an element (referred to as a pull-down resistor), as a result whereof a higher surface requirement results overall.
The active resistor, which is preferably realized by means of a PMOS transistor, in fact has a smaller area than the passive resistor butxe2x80x94as the upper discharge curve in FIG. 4 showsxe2x80x94does not enable a nearly complete discharge of a capacitative circuit node. It, too, represents an additional load for the circuit in the supplied condition or, respectively, in the operating condition since a current always flows across it during operation. Further, the discharge time is proportional to the value of resistance of the channel of the transistor, a long discharge time resulting therefrom. In principle, every critical circuit node given this circuit also requires its own circuit element of this type, a rather high surface requirement in an integration deriving overall as a result thereof.
Finally, the circuit shown in FIG. 3 has the advantage that the capacitance of a circuit node can be approximately completely discharged. Due to an additional process step for the depletion MOS transistor, however, it is very expensive and can therefore not be cost-beneficially implemented in many low-cost semiconductor technologies. Due to the charge pump 24, moreover, the circuit is very complex.
It is therefore an object of the present invention to propose a circuit arrangement and a method for discharging at least one circuit node that enables a cost-beneficial integration and a nearly complete discharging of the at least one circuit node within a relatively short time.
According to the present invention, a circuit arrangement is provided for discharging at least one circuit node. An input and at least one output are provided together with at least one controllable resistor, a capacitor, and a diode. A first terminal of a controllable path of the controllable resistor is connected to the output. A second terminal of the controllable path of the controllable resistor is connected to the input. The terminal of the capacitor and a cathode of the diode are connected to a control terminal of the controllable resistor. An anode of the diode is connected to the input. An integrated circuit is also provided wherein at least one output is connected to at least one circuit node of the integrated circuit, and a voltage that derives from a voltage source of the integrated circuit is present at the input. In a method for discharging at least one circuit node, a charge is stored on the capacitor, a discharge of said charge being delayed even after a disconnect of a supply voltage; and wherein a controllable resistor is controlled such that after a disconnect of the supply voltage, the resistor is conducted for a predetermined time duration within which the circuit node discharge is nearly complete. Further advantageous embodiments, developments and aspects of the present invention derive from the specification and the accompanying drawings.